SP8855E
2.8GHz Parallel Load Professional Synthesiser
Data Sheet 291297 issue 3 Nov-11
DESCRIPTION
The SP8855E is one of a family of parallel load
synthesisers containing all the elements apart from the
loop amplifier to fabricate a PLL synthesis loop. Other
devices in the series are the SP8852 which is a fully
programmable device requiring two 16 bit words to set
the RF and reference counters, and the SP8854 which
has hard wired reference counter programming and
requires a single bit word to program the RF divider.
The SP8855E is intended for applications where a fixed
synthesiser frequency is required although it can also
be used where frequency selection is set by switches.
In general the device will be programmed by
connecting the programming pins to either V
CC
or
ground. Additional hard wired inputs can be used to
control the F
pd
and F
ref
outputs set the control direction
of the loop and select the phase detector gain. Another
input may be used to disable the phase detector output.
The device is available in ceramic J-leaded 44-lead
chip carrier. Ambient temperature ranges available are
shown in the ordering information.
Ordering Information
SP8855E/KG/HCAR (in
trays)
-55°C to +100°C 44J-lead Ceramic Chip Carrier
SP8855E/IG/HCAR (in
trays)
-40°C to +85°C 44J-lead Ceramic Chip Carrier
EQUIVALENT PARTS:
PS20855
FEATURES
•
•
•
•
•
•
•
•
•
2.8GHz Operating Frequency (IG GRADE)
Single 5V Supply Operation
High Comparison Frequency 50MHz
High Gain Phase Detector 1mA/rad
Programmable Phase Detector Gain
Zero "Dead Band" Phase Detector
Wide range of RF and Reference Divide
Ratios
Programming by Hard Wired Inputs
Low cost plastic package option
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Description
Input bus bit 10
Input bus bit 9
Input bus bit 8
Input bus bit 7
Input bus bit 6
Input bus bit 5
Input bus bit 4
Input bus bit 3
Input bus bit 2
Input bus bit 1
Input bus bit 0
0V (prescaler)
RF input
RF input
V
CC
+ 5V (prescaler)
V
EE
0V
Lock detect output
C-lock detect
Rset
Charge pump output
Charge pump ref.
F
ref
/F
pd
enable
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Description
Control Direction
F
pd*
F
ref*
+5V
Ref. osc capacitor
Ref in/XTAL
Reference bit 9
Reference bit 8
Reference bit 7
Reference bit 6
Reference bit 5
Reference bit 4
Reference bit 3
Reference bit 2
Reference bit 1
Reference bit 0
Phase Detect Enable
Phase Detect Gain 1
Phase Detect Gain 0
Input bus bit 13
Input bus bit 12
Input bus bit 11
Figure 1 - Pin connections - top view
HC
ABSOLUTE MAXIMUM RATINGS
Supply voltage
-0.3V to 6V
Storage temperature
-65 °C to +150°C
Operating temperature
-55°C to +100°C
Prescaler & reference Input Voltage 2.5V p-p
Data Inputs
VCC +0.3V
VEE -0.3V
Junction temperature +175°C (HC package)
*Fpd and Fref outputs are reversed using the Control Direction
input. The table above is correct when pin 23 is high.
Data Sheet 291297 issue 3
Plessey Semiconductors Ltd.
Design & Technology Centre, Delta 500, Delta Business Park, Great Western Way, Swindon, UK SN5 7XE
Tel: +44 1793 518000
Fax: +44 1793 518030
Web: www.plesseysemi.com
1
RF DIVIDER PROGRAMMING
B0
B2
B3
B13
7
6
5 4
3
2
Fpd
11 BIT
M
COUNTER
1
44 43 42
9
8
10
MODULS
CONTROL
11
3 BIT
A
COUNTER
Vcc + 5V
PRESCALER
RF INPUT
÷
8/9
0V PRESCALER
20
21
17
19
18
24
25
22
23
40
41
10 BIT REFERENCE DIVIDER
Fref
CHARGE PUMP OUTPUT
CHARGE PUMP REFERENCE
LOCK DET O/P
R set
C - LOCK DETECT
Fpd *
Fref *
Fpd / Fref ENABLE
CONTROL DIRECTION
PHASE DETECTOR GAIN 1
PHASE DETECTOR GAIN 0
PHASE DETECTOR ENABLE
26
+5V
26
V
EE
0V
PHASE
DETECTOR
39
Data Sheet 291297 issue 3
Plessey Semiconductors Ltd.
Design & Technology Centre, Delta 500, Delta Business Park, Great Western Way, Swindon, UK SN5 7XE
Tel: +44 1793 518000
Fax: +44 1793 518030
Web: www.plesseysemi.com
27
28
REFERENCE REFERENCE
CRYSTAL
CAPACITOR
38 37 36 35 34 33 32 31 30 29
BIT 0
BIT 9
REFERENCE
DIVIDER
PROGRAMMING
* Fpd and Fref outputs are reversed using the Control
Direction input. Diagram is correct when pin 23 is high.
SP8855E
2
Figure 2 - block diagram
SP8855E
PIN Description
PIN
1,2,3,4,5,6,7,8,9,10,11,42,43,44
Description
These pins are the data inputs used to set the RF divider ratio
(M.N+A). Open circuit = 1 (high) on these pins. Inputs are transparent into
the data buffers.
Balanced inputs to the RF pre-amplifier. For single ended operation the
signal is AC coupled into pin 13 with pin 14 AC decoupled to ground (or
vice -versa). Pins 13 and 14 are internally DC biased.
A current sink into this pin is enabled when the lock detect circuit indicates
lock. Used to give an external indication of phase lock.
A capacitor connected to this point determines the lock detect integrator time
constant and can be used to vary the sensitivity of the phase lock indicator.
An external resistor from Pin 19 to V
CC
sets the charge pump output current
The phase detector output is a single ended charge pump sourcing or
sinking current to the inverting input of an external loop filter.
Connected to the non-inverting input of the loop filter to set the optimum DC
bias.
Part of the data input bus. When this pin is logic HI the F
ref
and F
pd
outputs
are enabled. Open circuit = HI
This pin controls charge pump output direction. For Pin 23 HI the output
sinks current when F
pd
> F
ref
or when the RF phase leads Ref phase. For Pin
23 LO the relationship is reversed. (see table 2).
Changing the state of pin 23 reverses the pins on which Fref and Fpd output
occur. See pin 24 and Pin 25 below for details. Open circuit = HI.
RF divider output pulses. Fpd = RF input frequency /(M.N+A). Pulse width =
8 RF input cycles (1 cycle of the divide by 8 prescaler output).
Reference divider output pulses. Fref = Reference input frequency/R. Pulse
width = high period of Ref input.
Leave open circuit if an external reference is used. See fig. 5 for typical
connection for use as an onboard crystal oscillator.
This pin is the input buffer amplifier for an external reference signal. This
amplifier provides the active element if an onboard crystal oscillator is used.
These pins set the Reference divider ratio R. Open circuit = HI.
When this pin is HI the phase detector output is enable. Open circuit = HI.
These pins set the charge pump current multiplication factor (see table 1).
Open circuit = HI.
13, 14 (RF INPUT)
17 (LOCK DETECT INPUT)
18 (C-LOCK DETECT)
19 (Rset)
20 (CP OUTPUT)
21 (CP REF)
22 (F
ref
/F
pd
ENABLE
23 (CONTROL DIRECTION)
24
= F
pd
if Pin 23 is HI
= F
ref
if Pin 23 is LO
= F
ref
if Pin 23 is HI
25
27 (Reference Oscillator Capacitor)
28 (Ref IN/XTAL)
29,30,31,32,33,34,35,36,37,38
39 (Phase Detector ENABLE)
40, 41 (PD Gain)
Data Sheet 291297 issue 3
Plessey Semiconductors Ltd.
Design & Technology Centre, Delta 500, Delta Business Park, Great Western Way, Swindon, UK SN5 7XE
Tel: +44 1793 518000
Fax: +44 1793 518030
Web: www.plesseysemi.com
3
SP8855E
_____________________________________________________________________________
Electrical Characteristics
Guaranteed over the full temperature and supply voltage range (unless otherwise stated)
Temperature T
amb
for KG parts -55°C and +100°C, Temperature T
amb
for IG parts -40°C and +85°,
Supply Voltage = 4.75V and 5.25V
Conditions
Characteristics
Supply current15, 26
RF input sensitivity
RF division ratio
Reference division ratio
Comparison frequency
Reference input frequency
Reference input voltage
Fref/Fpd output voltage
high
Fred/Fpd output voltage
low
Lock detect output voltage
Charge pump current at
multiplication factor = 1
Charge pump current at
multiplication factor = 1.5
Charge pump current at
multiplication factor = 2.5
Charge pump current at
multiplication factor = 4.0
Input bus high logic level
Input bus low logic level
Input bus current source
Input bys current sink
Up down current matching
Charge pump reference
voltage
Charge pump reference
voltage
Rset current
Rset Voltage 19
Notes:
Pin
Min
180
13, 14
13,14,24
28, 25
28,24,25
28
28
24, 25
24, 25
17
19,20,21
19,20,21
19,20,21
19,20,21
1-11, 22
23, 29-44
1-11, 22
23,29-44
1-11,22
23,29-44
1-11, 22
23,29-44
20
21
21
19
VCC-1.6
0.5
1.6
±1.4
±2.0
±3.4
±5.4
3.5
10
630
-5.0
56
1
Value
Typ
240
Max
mA
+7.0
16383
1023
50
100
1200
- 0.8
- 1.4
300
±1.5
±2.3
±3.8
±6.1
500
±1.7
±2.5
±4.6
±6.5
2000
Units
dBm
100MHz to 2.8/2.7GHz See Fig. 3
MHz
MHz
mV p-p
Vwrt
VCC
Vwrt
VCC
mV
mA
mA
mA
mA
V
Reference division ratio
≥
2 at
frequencies >50MHz also see Note 1.
Sine Wave 10-100MHz
2.2K to 0V
2.2K to 0V
IOUT = 3mA
Vpin 20 = Vpin 21,
Ipin 19 = 1.6mA
Vpin 20 = Vpin 21,
Ipin 19 = 1.6mA
Vpin 20 = Vpin 21,
Ipin 19 = 1.6mA
Vpin 20 = Vpin 21,
Ipin 19 = 1.6mA
1
-200
10
±5
VCC-
0.5
V
µA
µA
%
V
V
VIN = 0V
VIN = VCC
Vpin 20 = Vpin 21,
Ipin 19 = 1.6mA
Ipin 19 =1.6mA
current multiplication factor = 1
Ipin 19 =1.6mA
current multiplication factor = 4
See Note 2
Ipin 19 = 1.6mA
2
V
mA
1. Lower reference frequencies may be used if slew rates are maintained.
2. Pin 19 current x multiplication factor must be less than 5mA if charge pump accuracy is to be
maintained.
Data Sheet 291297 issue 3
Plessey Semiconductors Ltd.
Design & Technology Centre, Delta 500, Delta Business Park, Great Western Way, Swindon, UK SN5 7XE
Tel: +44 1793 518000
Fax: +44 1793 518030
Web: www.plesseysemi.com
4
SP8855E
TYPICAL OVERLOAD
+20
+10
+7
GUARANTEED
OPERATING
WINDOW
-5
OPERATING
AREA FOR
'IG' PARTS
ONLY
-10
-20
TYPICAL SENSITIVITY
-30
100MHz
1GHz
2.7GHz 2.8GHz
2GHz
10GHz
INPUT DRIVE REQUIREMENTS
Figure 3 - SP8855E
+j1
+j0.5
+j2
Zo = 50Ω
+j0.2
0
1.1GHz
0.2
0.5
1
50MHz
2.5GHz
-j0.2
-j0.5
-j1
-j2
Figure 4 - R.F. input impedance
Data Sheet 291297 issue 3
Plessey Semiconductors Ltd.
Design & Technology Centre, Delta 500, Delta Business Park, Great Western Way, Swindon, UK SN5 7XE
Tel: +44 1793 518000
Fax: +44 1793 518030
Web: www.plesseysemi.com
5
